Samsung announced today that it has developed the industry's first 50-nanometer (nm) DDR2 DRAM (dynamic random access memory) chip, which will increase production efficiency from the 60nm level by 55 percent. The new 1-gigabit (Gb) DRAM incorporates advanced technologies such as three-dimensional (3D) transistor design and multi-layered dielectric technology, which greatly enhance performance and data storage capabilities.

Continued miniaturization of the overall memory circuit and an increasingly limited area of coverage within a wafer cell make it much harder to secure and sustain sufficient volumes of electrons. Adding to the 50nm design improvements, the SEG transistor introduces a multi-layered dielectric layer (ZrO2/Al2O3/ZrO2) to resolve weak electrical features. In addition, the new dielectric layer sustains higher volumes of electron to increase storage capacity, ensuring higher reliability in storing data.

The 1 Gb 50nm chip encompasses three generations of DRAM technology (70nm, 60nm and 50nm) in achieving the most advanced level yet for DRAM mass production. Samsung’s new 50nm process technology can be applied to a broad range of DRAM chips including graphics and mobile DRAM.